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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/LiKM04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hao_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Katkoori>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wai-Kei_Mak>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F966137.966139>
foaf:homepage <https://doi.org/10.1145/966137.966139>
dc:identifier DBLP journals/todaes/LiKM04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F966137.966139 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Power minimization algorithms for LUT-based FPGA technology mapping. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hao_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Katkoori>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wai-Kei_Mak>
swrc:number 1 (xsd:string)
swrc:pages 33-51 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/LiKM04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/LiKM04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes9.html#LiKM04>
rdfs:seeAlso <https://doi.org/10.1145/966137.966139>
dc:subject Delay minimization, FPGA, power optimization, technology mapping (xsd:string)
dc:title Power minimization algorithms for LUT-based FPGA technology mapping. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 9 (xsd:string)