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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/LiLMSSHH23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arvind_K._Sharma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Meghna_Madhusudan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ramesh_Harjani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yaguang_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yishuang_Lin>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3559542>
foaf:homepage <https://doi.org/10.1145/3559542>
dc:identifier DBLP journals/todaes/LiLMSSHH23 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3559542 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Performance-driven Wire Sizing for Analog Integrated Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arvind_K._Sharma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiang_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Meghna_Madhusudan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ramesh_Harjani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sachin_S._Sapatnekar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yaguang_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yishuang_Lin>
swrc:month March (xsd:string)
swrc:number 2 (xsd:string)
swrc:pages 19:1-19:23 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/LiLMSSHH23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/LiLMSSHH23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes28.html#LiLMSSHH23>
rdfs:seeAlso <https://doi.org/10.1145/3559542>
dc:title Performance-driven Wire Sizing for Analog Integrated Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 28 (xsd:string)