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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/LiLQSW03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._M._H._Walker>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wangqi_Qiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weiping_Shi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiang_Lu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhuo_Li_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F944027.944036>
foaf:homepage <https://doi.org/10.1145/944027.944036>
dc:identifier DBLP journals/todaes/LiLQSW03 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F944027.944036 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label A circuit level fault model for resistive bridges. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._M._H._Walker>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wangqi_Qiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weiping_Shi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiang_Lu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhuo_Li_0001>
swrc:number 4 (xsd:string)
swrc:pages 546-559 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/LiLQSW03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/LiLQSW03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes8.html#LiLQSW03>
rdfs:seeAlso <https://doi.org/10.1145/944027.944036>
dc:subject bridge faults, delay faults, fault models (xsd:string)
dc:title A circuit level fault model for resistive bridges. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 8 (xsd:string)