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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/LyseckySV06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Frank_Vahid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Greg_Stitt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roman_L._Lysecky>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1142980.1142986>
foaf:homepage <https://doi.org/10.1145/1142980.1142986>
dc:identifier DBLP journals/todaes/LyseckySV06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1142980.1142986 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Warp Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Frank_Vahid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Greg_Stitt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roman_L._Lysecky>
swrc:number 3 (xsd:string)
swrc:pages 659-681 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/LyseckySV06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/LyseckySV06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes11.html#LyseckySV06>
rdfs:seeAlso <https://doi.org/10.1145/1142980.1142986>
dc:subject FPGA, Warp processors, configurable logic, dynamic optimization, hardware/software codesign, hardware/software partitioning, just-in-time (JIT) compilation (xsd:string)
dc:title Warp Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 11 (xsd:string)