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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/MiddelhoekR96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_F._A._Middelhoek>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sreeranga_P._Rajan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F233539.233541>
foaf:homepage <https://doi.org/10.1145/233539.233541>
dc:identifier DBLP journals/todaes/MiddelhoekR96 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F233539.233541 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label From VHDL to efficient and first-time-right designs: a formal approach. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_F._A._Middelhoek>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sreeranga_P._Rajan>
swrc:number 2 (xsd:string)
swrc:pages 205-250 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/MiddelhoekR96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/MiddelhoekR96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes1.html#MiddelhoekR96>
rdfs:seeAlso <https://doi.org/10.1145/233539.233541>
dc:subject CDFG, SFG, VHDL, correctness by construction, design methodology, rapid system prototyping, transformational design (xsd:string)
dc:title From VHDL to efficient and first-time-right designs: a formal approach. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 1 (xsd:string)