Power-delay optimization in VLSI microprocessors by wire spacing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/MoiseevKW09
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2009
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Power-delay optimization in VLSI microprocessors by wire spacing.
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dc:
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Wire spacing, delay-optimization, interconnect optimization, power optimization
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title
Power-delay optimization in VLSI microprocessors by wire spacing.
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