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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/PanL98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._L._Liu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peichen_Pan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F293625.293632>
foaf:homepage <https://doi.org/10.1145/293625.293632>
dc:identifier DBLP journals/todaes/PanL98 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F293625.293632 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Optimal clock period FPGA technology mapping for sequential circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._L._Liu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peichen_Pan>
swrc:number 3 (xsd:string)
swrc:pages 437-462 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/PanL98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/PanL98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes3.html#PanL98>
rdfs:seeAlso <https://doi.org/10.1145/293625.293632>
dc:subject FPGAs, clock period, field-programmable gate arrays, logic replication, look-up tables, retiming, sequential synthesis, technology mapping (xsd:string)
dc:title Optimal clock period FPGA technology mapping for sequential circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 3 (xsd:string)