System-level PVT variation-aware power exploration of on-chip communication architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/PasrichaPDK09
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2009
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System-level PVT variation-aware power exploration of on-chip communication architectures.
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dc:
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PVT variation, digital systems, high-level synthesis, on-chip communication architectures, performance exploration, power estimation
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System-level PVT variation-aware power exploration of on-chip communication architectures.
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