High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/PaulTC05
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2005
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High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.
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3
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431-461
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Computer-aided design, heterogeneous multiprocessors, performance modeling, schedulers, system modeling
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High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors.
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