Evolution of synthetic RTL benchmark circuits with predefined testability.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/PecenkaSK08
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2008
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Evolution of synthetic RTL benchmark circuits with predefined testability.
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Benchmark circuit, evolvable hardware, testability analysis
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Evolution of synthetic RTL benchmark circuits with predefined testability.
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