ATM switch design by high-level modeling, formal verification and high-level synthesis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/RajanFYL98
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1998
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ATM switch design by high-level modeling, formal verification and high-level synthesis.
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ATM switch, high-level design, synthesis, verification
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ATM switch design by high-level modeling, formal verification and high-level synthesis.
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