Event propagation for accurate circuit delay calculation using SAT.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/RoyCD07
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/todaes/RoyCD07
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Pallab_Dasgupta
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Suchismita_Roy
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1145%2F1255456.1255473
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homepage
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dc:
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DBLP journals/todaes/RoyCD07
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dc:
identifier
DOI doi.org%2F10.1145%2F1255456.1255473
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dcterms:
issued
2007
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swrc:
journal
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https://dblp.l3s.de/d2r/resource/journals/todaes
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rdfs:
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Event propagation for accurate circuit delay calculation using SAT.
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foaf:
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swrc:
number
3
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swrc:
pages
36:1-36:23
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owl:
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rdfs:
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seeAlso
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dc:
subject
Critical delay, SAT, event propagation
(xsd:string)
dc:
title
Event propagation for accurate circuit delay calculation using SAT.
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12
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