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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/RoyPKC05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arnab_Roy_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._P._Chakrabarti_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajeev_Kumar_0004>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Subrat_Kumar_Panda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1080334.1080336>
foaf:homepage <https://doi.org/10.1145/1080334.1080336>
dc:identifier DBLP journals/todaes/RoyPKC05 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1080334.1080336 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label A framework for systematic validation and debugging of pipeline simulators. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arnab_Roy_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._P._Chakrabarti_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajeev_Kumar_0004>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Subrat_Kumar_Panda>
swrc:number 3 (xsd:string)
swrc:pages 462-491 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/RoyPKC05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/RoyPKC05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes10.html#RoyPKC05>
rdfs:seeAlso <https://doi.org/10.1145/1080334.1080336>
dc:subject Simulation-based verification, dataflow equivalence, design space exploration, instruction scheduling, pipeline validation, pipelined architectures (xsd:string)
dc:title A framework for systematic validation and debugging of pipeline simulators. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 10 (xsd:string)