Instruction-level test methodology for CPU core self-testing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/ShamshiriEN05
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/todaes/ShamshiriEN05
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Hadi_Esmaeilzadeh
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Saeed_Shamshiri
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1145%2F1109118.1109124
>
foaf:
homepage
<
https://doi.org/10.1145/1109118.1109124
>
dc:
identifier
DBLP journals/todaes/ShamshiriEN05
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1145%2F1109118.1109124
(xsd:string)
dcterms:
issued
2005
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/todaes
>
rdfs:
label
Instruction-level test methodology for CPU core self-testing.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Hadi_Esmaeilzadeh
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Saeed_Shamshiri
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi
>
swrc:
number
4
(xsd:string)
swrc:
pages
673-689
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/todaes/ShamshiriEN05/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/todaes/ShamshiriEN05
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/todaes/todaes10.html#ShamshiriEN05
>
rdfs:
seeAlso
<
https://doi.org/10.1145/1109118.1109124
>
dc:
subject
BIST, CPU core testing, Instruction level testing, pipelined processor, software-based self testing, test instruction set
(xsd:string)
dc:
title
Instruction-level test methodology for CPU core self-testing.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
10
(xsd:string)