[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/ShaoXXZS06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bin_Xiao_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun_Xue>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Edwin_Hsing-Mean_Sha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qingfeng_Zhuge>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zili_Shao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1124713.1124724>
foaf:homepage <https://doi.org/10.1145/1124713.1124724>
dc:identifier DBLP journals/todaes/ShaoXXZS06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1124713.1124724 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Loop scheduling with timing and switching-activity minimization for VLIW DSP. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bin_Xiao_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun_Xue>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Edwin_Hsing-Mean_Sha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qingfeng_Zhuge>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zili_Shao>
swrc:number 1 (xsd:string)
swrc:pages 165-185 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/ShaoXXZS06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/ShaoXXZS06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes11.html#ShaoXXZS06>
rdfs:seeAlso <https://doi.org/10.1145/1124713.1124724>
dc:subject VLIW, compilers, instruction bus optimization, instruction scheduling, loops, low-power optimization, retiming, software pipelining (xsd:string)
dc:title Loop scheduling with timing and switching-activity minimization for VLIW DSP. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 11 (xsd:string)