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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/SongCKLH23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chien-Nan_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chih-Yun_Chou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Juinn-Dar_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ling-Yen_Song>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tung-Chieh_Kuo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3567422>
foaf:homepage <https://doi.org/10.1145/3567422>
dc:identifier DBLP journals/todaes/SongCKLH23 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3567422 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chien-Nan_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chih-Yun_Chou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Juinn-Dar_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ling-Yen_Song>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tung-Chieh_Kuo>
swrc:month March (xsd:string)
swrc:number 2 (xsd:string)
swrc:pages 18:1-18:22 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/SongCKLH23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/SongCKLH23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes28.html#SongCKLH23>
rdfs:seeAlso <https://doi.org/10.1145/3567422>
dc:title Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 28 (xsd:string)