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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/TsengJ99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jing-Yang_Jou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jyh-Mou_Tseng>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F298865.298869>
foaf:homepage <https://doi.org/10.1145/298865.298869>
dc:identifier DBLP journals/todaes/TsengJ99 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F298865.298869 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Two-level logic minimization for low power. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jing-Yang_Jou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jyh-Mou_Tseng>
swrc:number 1 (xsd:string)
swrc:pages 52-69 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/TsengJ99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/TsengJ99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes4.html#TsengJ99>
rdfs:seeAlso <https://doi.org/10.1145/298865.298869>
dc:subject logic synthesis, low power design, programmable logic array, two-level logic minimization (xsd:string)
dc:title Two-level logic minimization for low power. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 4 (xsd:string)