Power reduction and power-delay trade-offs using logic transformations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/WangVYG99
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1999
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Power reduction and power-delay trade-offs using logic transformations.
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97-121
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CMOS logic, logic optimization, logic synthesis, low power, power estimation
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Power reduction and power-delay trade-offs using logic transformations.
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