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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/todaes/YuHH09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hao_Yu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joanna_Ho>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lei_He_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1529255.1529263>
foaf:homepage <https://doi.org/10.1145/1529255.1529263>
dc:identifier DBLP journals/todaes/YuHH09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1529255.1529263 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/todaes>
rdfs:label Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hao_Yu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joanna_Ho>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lei_He_0001>
swrc:number 3 (xsd:string)
swrc:pages 41:1-41:31 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/todaes/YuHH09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/todaes/YuHH09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/todaes/todaes14.html#YuHH09>
rdfs:seeAlso <https://doi.org/10.1145/1529255.1529263>
dc:subject Thermal and power integrity, macromodeling, parametric 3D-IC design (xsd:string)
dc:title Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 14 (xsd:string)