Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/todaes/YuHH09
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Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.
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Thermal and power integrity, macromodeling, parametric 3D-IC design
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Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.
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