A parallel block implementation of Level-3 BLAS for MIMD vector processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/toms/DaydeDP94
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A parallel block implementation of Level-3 BLAS for MIMD vector processors.
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Level-3 BLAS, matrix-matrix kernels, parallelization, vectorization
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A parallel block implementation of Level-3 BLAS for MIMD vector processors.
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