[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/toplas/BreuerKLMF97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9s_Mar%E2%88%9A%E2%89%A0n_L%E2%88%9A%E2%89%A5pez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Carlos_Delgado_Kloos>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luis_S%E2%88%9A%C2%B0nchez_Fern%E2%88%9A%C2%B0ndez_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Natividad_Mart%E2%88%9A%E2%89%A0nez_Madrid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_T._Breuer>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F262004.262007>
foaf:homepage <https://doi.org/10.1145/262004.262007>
dc:identifier DBLP journals/toplas/BreuerKLMF97 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F262004.262007 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/toplas>
rdfs:label A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andr%E2%88%9A%C2%A9s_Mar%E2%88%9A%E2%89%A0n_L%E2%88%9A%E2%89%A5pez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Carlos_Delgado_Kloos>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luis_S%E2%88%9A%C2%B0nchez_Fern%E2%88%9A%C2%B0ndez_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Natividad_Mart%E2%88%9A%E2%89%A0nez_Madrid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_T._Breuer>
swrc:number 4 (xsd:string)
swrc:pages 585-616 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/toplas/BreuerKLMF97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/toplas/BreuerKLMF97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/toplas/toplas19.html#BreuerKLMF97>
rdfs:seeAlso <https://doi.org/10.1145/262004.262007>
dc:subject VHDL, denotational semantics, digital circuits, formal verification, program logic, refinement, timed logic (xsd:string)
dc:title A Refinement Calculus for the Synthesis of Verified Hardware Descriptions in VHDL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 19 (xsd:string)