Integrated Performance Models for SPMD Applications and MIMD Architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tpds/CremonesiG02a
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tpds/CremonesiG02a
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Claudio_Gennaro
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Paolo_Cremonesi
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http://dx.doi.org/doi.org%2F10.1109%2FTPDS.2002.1158268
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DBLP journals/tpds/CremonesiG02a
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dc:
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DOI doi.org%2F10.1109%2FTPDS.2002.1158268
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dcterms:
issued
2002
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Integrated Performance Models for SPMD Applications and MIMD Architectures.
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swrc:
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12
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swrc:
pages
1320-1332
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rdfs:
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dc:
subject
Single program multiple data (SPMD), multiple instruction multiple data (MIMD), performance model, queuing network model, fork-join queues, mean value analysis (MVA), parallel I/O, synchronization overhead, speedup surface.
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dc:
title
Integrated Performance Models for SPMD Applications and MIMD Architectures.
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13
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