A Design Methodology for Efficient Application-Specific On-Chip Interconnects.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tpds/HoP06
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http://dblp.uni-trier.de/rec/bibtex/journals/tpds/HoP06
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https://dblp.l3s.de/d2r/resource/authors/Wai_Hong_Ho
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http://dx.doi.org/doi.org%2F10.1109%2FTPDS.2006.15
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2006
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A Design Methodology for Efficient Application-Specific On-Chip Interconnects.
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2
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174-190
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dc:
subject
On-chip interconnects, communication model, low-contention communication, network partitioning, irregular topology.
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dc:
title
A Design Methodology for Efficient Application-Specific On-Chip Interconnects.
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