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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tpds/HsiaoC92>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._Y._Roger_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shuo-Hsien_Hsiao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F71.159047>
foaf:homepage <https://doi.org/10.1109/71.159047>
dc:identifier DBLP journals/tpds/HsiaoC92 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F71.159047 (xsd:string)
dcterms:issued 1992 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tpds>
rdfs:label Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._Y._Roger_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shuo-Hsien_Hsiao>
swrc:number 5 (xsd:string)
swrc:pages 632-640 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tpds/HsiaoC92/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tpds/HsiaoC92>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tpds/tpds3.html#HsiaoC92>
rdfs:seeAlso <https://doi.org/10.1109/71.159047>
dc:subject message size; circuit switched multistage interconnection networks; hold strategy;performance evaluation; processor-memory communications; multiprocessor systems;processor processing time; closed queuing network model; memory access;multiprocessor interconnection networks; performance evaluation; queueing theory;switching theory (xsd:string)
dc:title Performance Evaluation of Circuit Switched Multistage Interconnection Networks Using a Hold Strategy. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 3 (xsd:string)