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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tpds/PretePR95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cosimo_Antonio_Prete>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gianpaolo_Prina>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luigi_M._Ricciardi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F71.466630>
foaf:homepage <https://doi.org/10.1109/71.466630>
dc:identifier DBLP journals/tpds/PretePR95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F71.466630 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tpds>
rdfs:label A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cosimo_Antonio_Prete>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gianpaolo_Prina>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luigi_M._Ricciardi>
swrc:number 9 (xsd:string)
swrc:pages 915-929 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tpds/PretePR95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tpds/PretePR95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tpds/tpds6.html#PretePR95>
rdfs:seeAlso <https://doi.org/10.1109/71.466630>
dc:subject Cache memory, multiple cache consistency, coherence protocol, multiprocessor, performance analysis, trace-driven simulation. (xsd:string)
dc:title A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)