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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tpds/SihL93>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Edward_A._Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gilbert_C._Sih>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F71.207593>
foaf:homepage <https://doi.org/10.1109/71.207593>
dc:identifier DBLP journals/tpds/SihL93 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F71.207593 (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tpds>
rdfs:label A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Edward_A._Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gilbert_C._Sih>
swrc:number 2 (xsd:string)
swrc:pages 175-187 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tpds/SihL93/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tpds/SihL93>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tpds/tpds4.html#SihL93>
rdfs:seeAlso <https://doi.org/10.1109/71.207593>
dc:subject spatial dimensions; compile-time scheduling heuristic; interconnection-constrainedheterogeneous processor architectures; dynamic level scheduling; communicating tasks;temporal dimensions; parallel architectures; scheduling (xsd:string)
dc:title A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 4 (xsd:string)