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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tpds/TsueiV92>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mary_K._Vernon>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thin-Fong_Tsuei>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F71.180626>
foaf:homepage <https://doi.org/10.1109/71.180626>
dc:identifier DBLP journals/tpds/TsueiV92 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F71.180626 (xsd:string)
dcterms:issued 1992 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tpds>
rdfs:label A Multiprocessor Bus Design Model Validated by System Measurement. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mary_K._Vernon>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thin-Fong_Tsuei>
swrc:number 6 (xsd:string)
swrc:pages 712-727 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tpds/TsueiV92/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tpds/TsueiV92>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tpds/tpds3.html#TsueiV92>
rdfs:seeAlso <https://doi.org/10.1109/71.180626>
dc:subject system measurement; commercial multiprocessor bus; bus design; asynchronous memorywrite operations; in-order delivery; processor read requests; priority scheduling; memoryresponses; outstanding processor requests; two-level hierarchical model; Markov chain;mean value analysis techniques; queueing networks; measured system performance;parallel program workloads; memory access characteristics; analytic queueing models;model tractability; detailed simulation; system design tradeoffs; formal verification;Markov processes; multiprocessing systems; parallel programming; performanceevaluation; queueing theory; system buses (xsd:string)
dc:title A Multiprocessor Bus Design Model Validated by System Measurement. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 3 (xsd:string)