A Pairwise Substitutional Fault Tolerance Technique for the Cube-Connected Cycles Architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tpds/TzengC94
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1994
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A Pairwise Substitutional Fault Tolerance Technique for the Cube-Connected Cycles Architecture.
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4
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433-438
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dc:
subject
multiprocessor interconnection networks; fault tolerant computing; VLSI; fault tolerance;cube-connected cycles architecture; CCC; fault-tolerant CCC structure; fault-tolerantstructure; performance degradation; layout area; reconfiguration; reliability analysis; VLSI layout
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A Pairwise Substitutional Fault Tolerance Technique for the Cube-Connected Cycles Architecture.
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