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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tpds/ZhuoMP07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerald_R._Morris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ling_Zhuo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTPDS.2007.1068>
foaf:homepage <https://doi.org/10.1109/TPDS.2007.1068>
dc:identifier DBLP journals/tpds/ZhuoMP07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTPDS.2007.1068 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tpds>
rdfs:label High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerald_R._Morris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ling_Zhuo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Viktor_K._Prasanna>
swrc:number 10 (xsd:string)
swrc:pages 1377-1392 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tpds/ZhuoMP07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tpds/ZhuoMP07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tpds/tpds18.html#ZhuoMP07>
rdfs:seeAlso <https://doi.org/10.1109/TPDS.2007.1068>
dc:subject G.1.0.g Parallel algorithms, C.3.e Reconfigurable hardware (xsd:string)
dc:title High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 18 (xsd:string)