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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/trets/JangCCM09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alan_Mishchenko>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Billy_Chan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kevin_Chung>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_Jang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1534916.1534924>
foaf:homepage <https://doi.org/10.1145/1534916.1534924>
dc:identifier DBLP journals/trets/JangCCM09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1534916.1534924 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/trets>
rdfs:label WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alan_Mishchenko>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Billy_Chan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kevin_Chung>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_Jang>
swrc:number 2 (xsd:string)
swrc:pages 14:1-14:24 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/trets/JangCCM09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/trets/JangCCM09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/trets/trets2.html#JangCCM09>
rdfs:seeAlso <https://doi.org/10.1145/1534916.1534924>
dc:subject FPGA, area flow, cut enumeration, edge flow, technology mapping (xsd:string)
dc:title WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 2 (xsd:string)