Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/trets/MatsumotoHKKTNS08
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Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.
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FPGA, configuration, timing yield, within-die variation
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Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations.
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