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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/trets/Parandeh-AfsharBI09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hadi_Parandeh-Afshar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Ienne>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_Brisk>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1575774.1575778>
foaf:homepage <https://doi.org/10.1145/1575774.1575778>
dc:identifier DBLP journals/trets/Parandeh-AfsharBI09 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1575774.1575778 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/trets>
rdfs:label An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hadi_Parandeh-Afshar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Ienne>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_Brisk>
swrc:number 3 (xsd:string)
swrc:pages 19:1-19:42 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/trets/Parandeh-AfsharBI09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/trets/Parandeh-AfsharBI09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/trets/trets2.html#Parandeh-AfsharBI09>
rdfs:seeAlso <https://doi.org/10.1145/1575774.1575778>
dc:title An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 2 (xsd:string)