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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/trets/SaniY24>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andy_Gean_Ye>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sajjad_Rostami_Sani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3639055>
foaf:homepage <https://doi.org/10.1145/3639055>
dc:identifier DBLP journals/trets/SaniY24 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3639055 (xsd:string)
dcterms:issued 2024 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/trets>
rdfs:label Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andy_Gean_Ye>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sajjad_Rostami_Sani>
swrc:month March (xsd:string)
swrc:number 1 (xsd:string)
swrc:pages 17:1-17:29 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/trets/SaniY24/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/trets/SaniY24>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/trets/trets17.html#SaniY24>
rdfs:seeAlso <https://doi.org/10.1145/3639055>
dc:title Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 17 (xsd:string)