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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/trets/SedcoleC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/N._Pete_Sedcole>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1371579.1371582>
foaf:homepage <https://doi.org/10.1145/1371579.1371582>
dc:identifier DBLP journals/trets/SedcoleC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1371579.1371582 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/trets>
rdfs:label Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/N._Pete_Sedcole>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Peter_Y._K._Cheung>
swrc:number 2 (xsd:string)
swrc:pages 10:1-10:28 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/trets/SedcoleC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/trets/SedcoleC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/trets/trets1.html#SedcoleC08>
rdfs:seeAlso <https://doi.org/10.1145/1371579.1371582>
dc:subject Delay, FPGA, modeling, process variation, reconfiguration, statistical theory, within-die variability, yield (xsd:string)
dc:title Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 1 (xsd:string)