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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/trets/VestiasDSN23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hor%E2%88%9A%C2%B0cio_C._Neto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_T._de_Sousa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/M%E2%88%9A%C2%B0rio_P._V%E2%88%9A%C2%A9stias>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rui_Policarpo_Duarte>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3546182>
foaf:homepage <https://doi.org/10.1145/3546182>
dc:identifier DBLP journals/trets/VestiasDSN23 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3546182 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/trets>
rdfs:label Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hor%E2%88%9A%C2%B0cio_C._Neto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_T._de_Sousa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/M%E2%88%9A%C2%B0rio_P._V%E2%88%9A%C2%A9stias>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rui_Policarpo_Duarte>
swrc:month March (xsd:string)
swrc:number 1 (xsd:string)
swrc:pages 13:1-13:36 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/trets/VestiasDSN23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/trets/VestiasDSN23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/trets/trets16.html#VestiasDSN23>
rdfs:seeAlso <https://doi.org/10.1145/3546182>
dc:title Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)