An architecture for a DSP field-programmable gate array. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/M._Agarwala>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Poras_T._Balsara>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2F92.365460>
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dc:identifier	DBLP journals/tvlsi/AgarwalaB95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2F92.365460 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
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rdfs:label	An architecture for a DSP field-programmable gate array. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/M._Agarwala>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Poras_T._Balsara>
swrc:number	1 (xsd:string)
swrc:pages	136-141 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi3.html#AgarwalaB95>
rdfs:seeAlso	<https://doi.org/10.1109/92.365460>
dc:title	An architecture for a DSP field-programmable gate array. (xsd:string)
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swrc:volume	3 (xsd:string)