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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/AmiraC07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abbes_Amira>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shrutisagar_Chandrasekaran>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2007.893606>
foaf:homepage <https://doi.org/10.1109/TVLSI.2007.893606>
dc:identifier DBLP journals/tvlsi/AmiraC07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2007.893606 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abbes_Amira>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shrutisagar_Chandrasekaran>
swrc:number 3 (xsd:string)
swrc:pages 286-295 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/AmiraC07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/AmiraC07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi15.html#AmiraC07>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2007.893606>
dc:title Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)