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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/ChangCCWC15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bo-Wei_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chung-Hsien_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jhing-Fa_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shi-Huang_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yu-Hao_Chiu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2014.2305699>
foaf:homepage <https://doi.org/10.1109/TVLSI.2014.2305699>
dc:identifier DBLP journals/tvlsi/ChangCCWC15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2014.2305699 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bo-Wei_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chung-Hsien_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jhing-Fa_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shi-Huang_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yu-Hao_Chiu>
swrc:number 2 (xsd:string)
swrc:pages 230-243 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/ChangCCWC15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/ChangCCWC15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#ChangCCWC15>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2014.2305699>
dc:title Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)