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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/ChangRL03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Feipei_Lai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shanq-Jang_Ruan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yen-Jen_Chang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2003.812292>
foaf:homepage <https://doi.org/10.1109/TVLSI.2003.812292>
dc:identifier DBLP journals/tvlsi/ChangRL03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2003.812292 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Design and analysis of low-power cache using two-level filter scheme. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Feipei_Lai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shanq-Jang_Ruan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yen-Jen_Chang>
swrc:number 4 (xsd:string)
swrc:pages 568-580 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/ChangRL03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/ChangRL03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi11.html#ChangRL03>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2003.812292>
dc:title Design and analysis of low-power cache using two-level filter scheme. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 11 (xsd:string)