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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/DasygenisBDCST06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Adonios_Thanailakis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bart_Durinck>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Soudris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Erik_Brockmeyer>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francky_Catthoor>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Minas_Dasygenis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2006.871759>
foaf:homepage <https://doi.org/10.1109/TVLSI.2006.871759>
dc:identifier DBLP journals/tvlsi/DasygenisBDCST06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2006.871759 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Adonios_Thanailakis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bart_Durinck>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Soudris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Erik_Brockmeyer>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francky_Catthoor>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Minas_Dasygenis>
swrc:number 3 (xsd:string)
swrc:pages 279-291 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/DasygenisBDCST06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/DasygenisBDCST06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi14.html#DasygenisBDCST06>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2006.871759>
dc:title A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 14 (xsd:string)