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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/DattaBCMR08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Animesh_Datta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jung_Hwan_Choi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Swarup_Bhunia>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2008.2000364>
foaf:homepage <https://doi.org/10.1109/TVLSI.2008.2000364>
dc:identifier DBLP journals/tvlsi/DattaBCMR08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2008.2000364 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Profit Aware Circuit Design Under Process Variations Considering Speed Binning. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Animesh_Datta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jung_Hwan_Choi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Swarup_Bhunia>
swrc:number 7 (xsd:string)
swrc:pages 806-815 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/DattaBCMR08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/DattaBCMR08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#DattaBCMR08>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2008.2000364>
dc:title Profit Aware Circuit Design Under Process Variations Considering Speed Binning. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)