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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/GaitanGU15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ioan_Ungurean>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nicoleta-Cristina_Gaitan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vasile_Gheorghita_Gaitan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2014.2346542>
foaf:homepage <https://doi.org/10.1109/TVLSI.2014.2346542>
dc:identifier DBLP journals/tvlsi/GaitanGU15 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2014.2346542 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ioan_Ungurean>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nicoleta-Cristina_Gaitan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vasile_Gheorghita_Gaitan>
swrc:number 9 (xsd:string)
swrc:pages 1661-1674 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/GaitanGU15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/GaitanGU15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi23.html#GaitanGU15>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2014.2346542>
dc:title CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)