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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/GalaBZVJ02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anil_Joshi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_T._Blaauw>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Gala>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pravin_M._Vaidya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vladimir_Zolotov>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2002.801619>
foaf:homepage <https://doi.org/10.1109/TVLSI.2002.801619>
dc:identifier DBLP journals/tvlsi/GalaBZVJ02 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2002.801619 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Inductance model and analysis methodology for high-speed on-chip interconnect. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anil_Joshi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_T._Blaauw>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Gala>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pravin_M._Vaidya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vladimir_Zolotov>
swrc:number 6 (xsd:string)
swrc:pages 730-745 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/GalaBZVJ02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/GalaBZVJ02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi10.html#GalaBZVJ02>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2002.801619>
dc:title Inductance model and analysis methodology for high-speed on-chip interconnect. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 10 (xsd:string)