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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/JeyasinghBA11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bharadwaj_S._Amrutur>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Navakanta_Bhat>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rakesh_Gnana_David_Jeyasingh>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2009.2031650>
foaf:homepage <https://doi.org/10.1109/TVLSI.2009.2031650>
dc:identifier DBLP journals/tvlsi/JeyasinghBA11 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2009.2031650 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bharadwaj_S._Amrutur>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Navakanta_Bhat>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rakesh_Gnana_David_Jeyasingh>
swrc:number 2 (xsd:string)
swrc:pages 295-304 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/JeyasinghBA11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/JeyasinghBA11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi19.html#JeyasinghBA11>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2009.2031650>
dc:title Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 19 (xsd:string)