A Methodology for Transistor-Efficient Supergate Design. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Dimitrios_Kagaris>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Themistoklis_Haniotakis>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2007.895248>
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dc:identifier	DBLP journals/tvlsi/KagarisH07 (xsd:string)
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dcterms:issued	2007 (xsd:gYear)
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swrc:pages	488-492 (xsd:string)
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dc:title	A Methodology for Transistor-Efficient Supergate Design. (xsd:string)
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