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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/KoBN98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Poras_T._Balsara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uming_Ko>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F92.678891>
foaf:homepage <https://doi.org/10.1109/92.678891>
dc:identifier DBLP journals/tvlsi/KoBN98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F92.678891 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Energy optimization of multilevel cache architectures for RISC and CISC processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Poras_T._Balsara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uming_Ko>
swrc:number 2 (xsd:string)
swrc:pages 299-308 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/KoBN98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/KoBN98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi6.html#KoBN98>
rdfs:seeAlso <https://doi.org/10.1109/92.678891>
dc:title Energy optimization of multilevel cache architectures for RISC and CISC processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)