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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/LaiWL07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/An-Yeu_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chien-Hsiung_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jyh-Ting_Lai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2007.893593>
foaf:homepage <https://doi.org/10.1109/TVLSI.2007.893593>
dc:identifier DBLP journals/tvlsi/LaiWL07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2007.893593 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/An-Yeu_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chien-Hsiung_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jyh-Ting_Lai>
swrc:number 2 (xsd:string)
swrc:pages 236-240 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/LaiWL07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/LaiWL07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi15.html#LaiWL07>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2007.893593>
dc:title Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)