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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/LiLW08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/An-Yeu_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cheng-Hung_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fan-Min_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2008.2000514>
foaf:homepage <https://doi.org/10.1109/TVLSI.2008.2000514>
dc:identifier DBLP journals/tvlsi/LiLW08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2008.2000514 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/An-Yeu_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cheng-Hung_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fan-Min_Li>
swrc:number 10 (xsd:string)
swrc:pages 1358-1371 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/LiLW08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/LiLW08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi16.html#LiLW08>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2008.2000514>
dc:title Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)