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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/LingLTSSY21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Yang_0006>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ke_Tan_0004>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming_Ling>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qingde_Lin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shan_Shen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianxiang_Shao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2021.3120653>
foaf:homepage <https://doi.org/10.1109/TVLSI.2021.3120653>
dc:identifier DBLP journals/tvlsi/LingLTSSY21 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2021.3120653 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Yang_0006>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ke_Tan_0004>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming_Ling>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qingde_Lin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shan_Shen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianxiang_Shao>
swrc:number 12 (xsd:string)
swrc:pages 2197-2209 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/LingLTSSY21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/LingLTSSY21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi29.html#LingLTSSY21>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2021.3120653>
dc:title A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 29 (xsd:string)