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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/ManohararajahCSB07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Deshanand_P._Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gordon_R._Chiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_Dean_Brown>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Valavan_Manohararajah>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTVLSI.2007.900744>
foaf:homepage <https://doi.org/10.1109/TVLSI.2007.900744>
dc:identifier DBLP journals/tvlsi/ManohararajahCSB07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTVLSI.2007.900744 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Deshanand_P._Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gordon_R._Chiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_Dean_Brown>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Valavan_Manohararajah>
swrc:number 8 (xsd:string)
swrc:pages 895-903 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/ManohararajahCSB07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/ManohararajahCSB07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi15.html#ManohararajahCSB07>
rdfs:seeAlso <https://doi.org/10.1109/TVLSI.2007.900744>
dc:title Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)